An important part of integrated circuit manufacture concerns "pattern transfer" or the implementation of a pattern, as defined by a masking layer that has been photolithographically patterned, in a film, layer or substrate by chemical or physical methods that produce surface relief. The various devices of an integrated circuit and the interconnections between them are formed by the interrelations of the various surface relief patterns.
Very large scale integration (VLSI) processes that are commonly used today in the manufacture of integrated circuits employ a subtractive method of pattern transfer. In subtractive pattern transfer, the layer to be etched is deposited first, and a masking layer, typically photoresist (although other materials are used), is then patterned photolithographically and the unwanted portions of the photoresist are removed by a chemical developer, thereby exposing the underlying layer to be etched. Finally, the exposed portions of the layer are etched away by physical or chemical means.
The resolution of an etching process is a measure of the fidelity of pattern transfer, which can be quantified by an etch bias quantity. Bias refers to the difference in lateral dimension between the etched image and the mask image. In the formula most commonly used at present, two parameters give the bias according to the equation B=(d.sub.m- d.sub.f), where B stands for the etch bias, d.sub.m is the length of a particular critical dimension (CD) as measured along the mask image made in the photoresist before any etching of the device feature layer and d.sub.f represents the final length of the CD measured along the surface of the etched layer.
A zero-bias process produces a vertical edge profile coincident with the edge of the mask. In other words, the mask, the etched device feature layer and the patterned photoresist would all be precisely aligned. In this case, there is no etching of the device feature layer or the photoresist in the lateral direction, and the pattern is perfectly transferred. This case represents the extreme of anisotropic etching. In VLSI processes, achieving an anisotropic etch can be very important in the manufacture of some devices. However, as a practical matter, a completely anisotropic etch is unachievable in many instances. Hence, measurement of bias is necessary to know how to compensate for the bias in the design of the photomask and the device fabrication process so that after the etch is completed the surface relief is as desired, with the bias being taken into account.
In VLSI device fabrication, there are stringent CD control requirements in plasma etching in particular. In general during plasma etch production and process development, calibrated optical measurement equipment is used to measure the selected critical dimension both before etch and after etch to determine the etch bias. However, the calibration of optical instruments involves a lengthy routine which is very sensitive to film thickness, etch profile, resist profile, program parameter settings, etc. Currently, it is common to use a scanning electron microscope (SEM) to aid in the calibration of the optical equipment. It would be desirable to have an etch bias determination technique that would not require such an extensive calibration procedure and which would eliminate some of the sensitivity to sources of error such as etch profile and resist profile. In addition, optical inspection of the resulting device features can only be accomplished by an inspection after the photoresist layer is removed because only vague and hazy lines may be seen if the device feature is inspected with the photoresist in place due to the semi-transparent or translucent nature of the photoresist material. In other words, the edge of the device feature after etch, with the photoresist in place, appears blurred from above by automatic and even visual inspection due to the light scattering caused by the edge of the remaining photoresist layer. The photoresist edge being beveled inward also contributes to the blurring effect.
Discussion of prior bias measurement techniques will be continued with reference to FIG. 2 of the drawings. Shown in FIG. 2A is a semiconductor device under construction 20 having a device feature layer 24 which has been formed upon semiconductor substrate 22. Previous to this step, a photoresist layer 28 has been formed over the device feature layer 24 and patterned by well-known photolithographic means, and the photoresist 28 has a dimension of d.sub.m which is measured from above optically according to the present technique.
At this stage, the physical or chemical etch of the device feature layer 24 is ready to occur. This etching gives a structure such as that seen in FIG. 2B, viewed from above as would be typical in an optical measurement procedure, where the device feature layer 24 has been formed having the dimension d.sub.f, which is reduced from the d.sub.m dimension. Note that photoresist feature 28 has been removed from FIG. 2B so that measurement d.sub.f may be determined. From FIG. 2B, the etch bias may be taken as B=(d.sub.m -d.sub.f). However, to obtain B, two separate measurements must be made of the semiconductor device under construction 20, since d.sub.m can only be measured from the FIG. 2A structure and d.sub.f can only be measured from the FIG. 2B structure. The dimension of d.sub.m shown on FIG. 2B in dashed lines is presented for comparison purposes only and would not be seen in any manner at this stage in the process. It would be desirable if an etch bias monitoring technique could be devised which would only require one examination step instead of two.
FIG. 2C illustrates in profile a particular situation that must be addressed by an etch bias monitoring technique, namely the situation where the device feature layer 24 etches away faster than and undercuts the photoresist layer 28. Here, B again equals (d.sub.m -d.sub.f). It is apparent that the etch bias cannot be determined optically by the method used in FIG. 2B with the photoresist 28 in place.
An additional problem concerns measuring the amount the photoresist layer 28 is etched back away from the mask edges (d.sub.m) and how this affects the etch bias of the device feature layer 24. Under the current optical inspection procedure, such a measurement would be very difficult.
The only possible approach would be to measure the photoresist layer 28 from above optically to obtain the CD measurement for the photoresist 28 remaining, if possible, and then remove the photoresist layer 28 and conduct an optical inspection to obtain d.sub.f to compare with d.sub.m from a previous measurement procedure. This optical measurement procedure would require three different measurement sessions, and would be of doubtful accuracy due to the blurring of the edges of the photoresist pattern 28 and device feature layer 24 mentioned earlier. Even if a SEM of the profile were made, all of the information required to determine the bias would still not be present for the d.sub.m parameter cannot be measured from the structure only seen in FIG. 2C. At least two measurement steps would again be required.